AMD planning to deliver Opteron Chips
with Steamroller cores
this year

Advanced Micro Devices
has released a
presentation for investors
that puts the launch of the
new Steamroller micro-
architecture in 2013.
One of the reasons why
dual-core Bulldozer
modules [the same may
be said about Piledriver]
are not completely
efficient is because they
have only one instruction
decoder for two ALUs and
one FPU. With steamroller,
AMD not only incorporated
two decoders per module,
but also increased
instruction cache size (to
lower i-cache misses by
30%), enhanced
instruction pre-fetch (the
number of mis-predicted
branches is down by 20%
compared to Bulldozer ) as
well as improved max-
width dispatches per
thread by 25%. AMD
believes that Steamroller
will provide 30%
improvement in ops per
AMD also advanced single-
core execution by
implementing 5%-10%
more efficient scheduling,
incorporated higher-
capacity register files and
performed some other