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Thread: Intel Haswell News And Discussion

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    Exclamation Intel Haswell News And Discussion

    Intel’s next-generation processor and the whole Haswell-EP platform is likely to be the biggest jump in performance since the 2006 introduction of Core 2 Duo. The Haswell processor itself will be considerably more advanced than Ivy Bridge, while bringing new innovative features and raw computing power.

    The Haswell processor will still be manufactured in 22 nm process, which confirms the fact that Intel is not going to reach 14 nm processor manufacturing during the next year.

    Intel’s new platform will most likely be the first DDR4 personal computing platform available on a large scale. The fastest DDR4 memory modules supported will be running at a modest 2133 MHz.

    We’re calling 2133 MHz modest because many memory manufactures have announced weeks – if not months – ago DDR3 modules certified to work at 3 GHz using overclocking settings.

    The company has always been conservative about the memory frequencies supported by its chipsets, so the Haswell-EP platforms will be no different this time.
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    Intel’s slide, published by ChipHell, clearly shows that the processor is supposed to have 10 or more processing cores.

    Moreover, if we take a look at the level 3 cache allocation, we’ll see that the chart also says that there will be roughly a 2.5 MB level 3 cache slice allocated to each core.

    Considering that there will be a total of 35 MB of level 3 cache, this amounts to about 14 cores, and that’s an impressive number in itself.

    AMD originally had 10-core processor plans for 2013, but those were scrapped once new management came in place.

    Sure, the small, fabless CPU designer can stick together two dies with 8 cores each, but that's a totally different approach when compared with Intel’s 35 MB shared level 3 cache.

    HyperThreading technology will still be around and Haswell will also come with HNI or Haswell New Instructions.

    That is an Intel AVX 2.0 set of instructions that the company will design inside its new processor.

    Source:http://news.softpedia.com/news/Intel...e-278198.shtml
    Last edited by VANGUARD; August 10th, 2012 at 04:08.

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    Processor er price e hobe 1 lakh

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    Its gonna blow away everything, just like sandy bridge.

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    1 m0nth por sunbo abar new processor astese....
    To be c0ntinued

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    Quote Originally Posted by Single_Player View Post
    1 m0nth por sunbo abar new processor astese....
    To be c0ntinued
    Not like that; Haswell is the "tock" technology of Intel's "Tick-Tock" roadmap, so the next processor Broadwell will just be a 14nm die shrinked version of Haswell. Just like Ivy Bridge. So, if you take a good HW processor in early '13, you are safely easy to rest until early '16, arrival of Skylake.

    - - - Updated - - -

    Quote Originally Posted by nirzhar View Post
    Processor er price e hobe 1 lakh
    No, it wont because Intel claims that the mass production cost of Haswell will be even lower than todays Sandy Bridge and the 10-12 core versions will be priced in the same range of todays mainstream scale; unless you want to buy a processor with 14 cores and 28 threads
    Last edited by VANGUARD; August 11th, 2012 at 14:45.

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    @vangaurd do you the mainstream processors will have more than 6 cores?? i dont know, haswell is sounding too good to be true.... i will need to read up on haswell b4 i get my expectations too high. what i like is that the 22nm process will have matured properly for the haswell by 2013. so thats a good news for sure. and it is the 'tock' in their production scheme so should be good.

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    Quote Originally Posted by zunaid View Post
    @vangaurd do you the mainstream processors will have more than 6 cores?? i dont know, haswell is sounding too good to be true.... i will need to read up on haswell b4 i get my expectations too high. what i like is that the 22nm process will have matured properly for the haswell by 2013. so thats a good news for sure. and it is the 'tock' in their production scheme so should be good.
    Hote pare, 6 cores with 12 threads. But oigula probably low end hobe. Mainstream 8-10 cores howa uchit, with 16-20 threads.

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    I would rather wait for graphene chips with terahrz technology.
    Soon these silicon fabs would reach their omega point.

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    Quote Originally Posted by Mohiuddin View Post
    I would rather wait for graphene chips with terahrz technology.
    Soon these silicon fabs would reach their omega point.
    Haswell GT3, mama, Haswell GT3. Sheirokom horny akta processor.

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    Nice...but I have to see the raw performance increase in real-life scenario before I feel tempted to upgrade from 3770k. Most likely, I'll go for the tick again.
    Last edited by CvP; August 11th, 2012 at 21:32.
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    Finally a true successor to SB!

    I do hope the prices stay the same as SB-Ivy, considering that they have no competition and Piledriver is shaping up to compete with SB, there are high chances they'll charge $350 for the mainstream processor.

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    Lightbulb Detailed info of Intel Haswell, Introducing DDR4 RAMs

    Memory Support:

    A certain DRAM major's frantic lobbying for the arrival of DDR4 seems to be paying off, as we're seeing some of the first leaks of information related to Intel's next-generation enterprise platform, Haswell-EP, slated for 2013-2014. Three crucial slides related to the platform component arrangement, the innards of the processor and core-logic themselves, were leaked. Haswell-EP will be built on the 22 nm silicon fabrication process, and will be perhaps the first platform to use DDR4 memory.

    The first and most important portion of a leaked slide reveals the arrangement of the various key components in the platform. It reveals an arrangement that is not much different from today's Sandy Bridge-EP platforms, in which n-number of CPU sockets are wired to each other using fast QuickPath Interconnect (QPI). Intel will use dual-channel QPI, which doubles bandwidth over what is available with today's enterprise platforms. Assuming each channel is clocked at 6.4 GT/s, the cumulative bandwidth would amount to 51.2 GB/s.


    Each socket will have four DDR4 DRAM channels. The DDR4 DRAM specification will introduce a fundamental change in the topology of DRAM components, which will be arranged "point-to-point". Each DRAM "channel" from the memory controller will support just one DRAM module, but there will be greater scope for DRAM makers to scale up densities of the modules with advancements in technology and silicon fabrication process. Much like Sandy Bridge-EP, Haswell-EP will see a bulk of the platform's PCI-Express lane budget being care of the processors' system agents; and will require external chipset for peripheral connectivity.

    One significant and much-required change here is that the chipset will not hold the GbE interfaces for the platform. It is estimated that 1 GbE would reach obsoletion, at least in the enterprise space, in which faster interfaces such as 10 GbE, or even InfiniBand would have become "common". Since these are extremely bandwidth-hungry interfaces, Intel restructured the platform in a way that "common" onboard network interface controllers will be wired to the PCI-Express root complexes of the processors, rather than the chipset.


    The Processor and Power Consumption:

    While the slides don't go into deep micro-architecture related details, it does give a fair idea of how things are arranged on the Haswell-EP die. The components on the chip are arranged much in the same way as they are, on Sandy Bridge-EP, only that the scale of things appear to have gone up. Oversimplified, the die consists of cores, their complementary slices of last-level cache (L3 cache), system agent, memory controller, PCI-Express root complex, and QPI root complex connected with a ring-bus. Components are enabled/disabled by controlling the "ring-stops" (points where the bus picks up or drops off data/instructions) for each of the components, to carve out the various SKUs based on the silicon.


    As mentioned earlier, 22 nm will be Intel's silicon fabrication process of choice, which will have matured quite a bit, when Haswell-EP's stint at the market arrives. While the diagram above doesn't give a clear picture about the number of cores Intel wants to cram onto the silicon, it's likely that there are 14 cores. One can deduce that looking at the total L3 cache amount mentioned (up to 35 MB), and amount of cache complementary to each core (around 2560 KB). That works out to 14 cores. Even in today's processor architectures by Intel, the L3 cache isn't a monolithic slab of SRAM, even though it is shared between all the cores. It consists of sub-divisions, which can be toggled to alter the amount L3 cache the various processor models end up with.

    The system agent performs most of the ancillary functions of the processor. The integrated memory controller (IMC) will support the new DDR4 DRAM specification, which enables greater speeds and higher densities at lower voltages. The Haswell-EP IMC supports quad-channel DDR4-2133 MHz. The PCI-Express root complex will be PCI-Express Gen 3.0 compliant, and will include 40 lanes on the Haswell-EP and 24 lanes on Haswell-EN.

    While every Haswell-EP processor comes with DMI, with which it can talk to the chipset, not every socket will be wired to the chipset. The sockets will be wired to each other in a kind of mesh-topology, using QPI links, and one of the processors will be wired to the chipset over DMI (and DMI-assisting PCI-Express links, if any).

    A few other features mentioned in the above slide include HyperThreading, per core P-state, uncore frequency scaling, a newer version of Turbo Boost, and an integrated VRM control logic, which is probably how Intel will mandate a new VRD specification without bothering about inconsistencies between the various motherboards with regards to VRM design, out in the market.

    The new processors will come with massive TDPs, in the range of 130~160 Watts.

    The Chipset:
    The next major component in the Haswell-EP platform is its chipset, codenamed "Wellsburg." It will be branded Intel C610 series platform hub. Intel will take advantage of a newer silicon fabrication process (32 nm sounds likely), to cram more components on the chipset's silicon, without making it larger. To that effect, Intel mentioned the package size of the C610 doesn't exceed 25 x 25 mm, and its TDP (at maximum load) doesn't exceed 7W.
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    The chipset integrates a clock generator, it can share this clock with other components on the platform, or even be configured to rely on external clock signal. In terms of storage connectivity, we see a greater proliferation of new generation interfaces, such as SATA revision 3.0 and USB 3.0 SuperSpeed. The chipset can drive no less than ten SATA 6 Gb/s ports, with enterprise Rapid Storage Technology (RSTe) RAID support, with optional SSD caching (similar to Smart Response Technology). The C610 "Wellsburg" chipset will also feature a new USB port load-out, with six USB 3.0 and eight USB 2.0 ports. The reminiscent of today's GbE LAN PHYs are still there with the chipset, although it's unlikely that mainstram server boards will use it. Entry level ones will probably still use a couple of GbE controllers.

    In conclusion, Haswell-EP looks like a monstrous concoction for enterprise platforms, with a focus on facilitating tomorrow's high bandwidth network interfaces.

    The source of the slides is ChipHell.

    Source:http://vr-zone.com/articles/intel-ha...d/16419-3.html

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    Threads merged and renamed. Use this for everything Haswell.

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    Quote Originally Posted by aayman View Post
    Threads merged and renamed. Use this for everything Haswell.
    Good Job!

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    Won't get the chance to settle with Ivy Bridge...........Now comes the Haswell................People are moving too fast, yet i'm stuck with my C2D............!!! What The ¤¤¤¤¤¤¤?????



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    sigh.... Ami r parmu na...... 6YRS DHORE AMI p4 er sathe asi!! Kal porshui ivy bridge room e ashtese.....

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    Quote Originally Posted by Vanguard View Post
    Not like that; Haswell is the "tick" technology of Intel's "Tick-Tock" roadmap, so the next processor Broadwell will just be a 14nm die shrinked version of Haswell. Just like Ivy Bridge. So, if you take a good HW processor in early '13, you are safely easy to rest until early '16, arrival of Skylake.
    i thought the ivy bridge was the 'tick' as its a die shrink and so naturally, the haswell would be the 'tock' as it is a new microarchitecture. Right?

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    Quote Originally Posted by zunaid View Post
    i thought the ivy bridge was the 'tick' as its a die shrink and so naturally, the haswell would be the 'tock' as it is a new microarchitecture. Right?
    Sandy was tock, Ivy was tick. Haswell is tock, Broadwell will be tick. All die shrinks are Tick.
    Last edited by VANGUARD; August 11th, 2012 at 14:44.

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    I hate to say this, but i think u are wrong on this one @Vanguard see here, the official intel 'tick tock' page.... 'tick tock' hehe... ingenious.... oh yes, the page... http://www.intel.com/content/www/us/...l-general.html

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    Quote Originally Posted by zunaid View Post
    I hate to say this, but i think u are wrong on this one @Vanguard see here, the official intel 'tick tock' page.... 'tick tock' hehe... ingenious.... oh yes, the page... http://www.intel.com/content/www/us/...l-general.html
    Oh yeah, you are right, revising it. How could i miss that! Probably watching too much p*** nowadays
    Last edited by VANGUARD; August 11th, 2012 at 14:46.

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