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Thread: Haswell News Thread!

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    Default Haswell News Thread!

    Haswell to launch in March - June 2013

    The latest Intel CPU roadmap has been seen at Donanimhaber, and shows that Haswell is currently expected to launch between March and June 2013. Using socket 1150, Haswell will be built using the same 22 nm production process as Ivy bridge. Interestingly, there is no sign of Ivy Bridge-E to replace Sandy Bridge-E for socket 2011 systems before the end of H1 2013, suggesting that SB-E may have quite an extended lifecycle.

    Haswell will support DDR3 and DDR3L at 1600 MHz. it is expected to have a TDP of between 35W and 95W, and to run at faster clock speeds (with easier overclocking) than Ivy Bridge. The high TDP (Ivy Bridge has a maximum TDP of 77W) is possibly down to a more powerful iGPU (although this is unconfirmed).

    There are conflicting reports about the performance and specs of the integrated graphics core. Known as the generation 7.5 graphics core, it is a minor upgrade to the graphics core used in Ivy Bridge. Ivy Bridge has up to 16 Execution Units (EU). Haswell has between 20 (VR-Zone) and 40 (SemiAccurate) 128-bit EU, with performance estimates ranging from 20% to 150% better than Ivy Bridge. Most sites refer to a graphics performance increase from Ivy Bridge to Haswell of somewhere in the region of 50%.

    Update (February 14, by Gennadiy Shvets): Yesterday Donanimhaber posted another Haswell slide, that highlights major new improvements in the microarchitecture. The slide confirms many of originally reported features, such as enhanced overclocking, new AES and AVX instructions, integrated voltage regulator, support for three independent displays, LGA 1150 socket, memory configurations, and 35W - 95W power envelope. The slide does not have any new information about the microarchitecture.

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    50% increase of IVB? .... r kisu bolar nai. At least one company knows how to release new products.

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    Hmmm....i guessed that power consumption will increase, because to provide more performance within the same 22nm Lithography simply needs more power. We have to wait until the 14nm Broadwell which will be released in early 2014.

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    Not necessarily because its dependent on the design also note that 22nm wouldnt really be an easy task to achive with out tri gate 3d transistors as die shrinks do enable us to contain the thermal package and shove in more transistors at a given space but it also has flaws such as electric leakage so without newer designs and optimization's a die shrink is not as easy as it seems. Also power consumption does not translate the output of the processors speed as if the given architecture is more efficient it will yield a higher performance at a lower power consumption and maybe even lower clockspeeds. Remember when AMD made a die shrink to 65nm they had huge problems with SOI going past the 3ghz mark on phenom 1 gen processors because of electric gate leakages



    Click image for larger version. 

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    Intel processors have started using HKMG (high K die electric metal gates) for its transistors thus overall leakage is reduced drastically.
    FTW!!!!!!!!!!

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    Transactional Synchronization Extensions in Haswell

    Intel have released details of their new Transaction Synchronization Extensions (TSX) programming model and instruction set that will be introduced with Haswell. These new extensions will help with synchronization of shared memory in multithreaded apps that use memory locks, by combining a lot of small locks into one large lock.

    Traditionally, programmers would lock just the small area of shared memory that is being worked on, with overheads for each lock/release operation. With TSX, it is the hardware, and not the software, which decides how threads should execute when using lock-protected shared memory, and they will be serialized only when it is needed. Instead of having the software request a separate lock for each thread that is working on an area of shared memory, the program can request that a larger area of memory be locked, and then run the threads as normal.

    If two or more threads try to operate on the same piece of data within that memory area, the processor will block them both, and then perform serialization as needed. Otherwise all the threads run as normal, without the normal overheads associated with locking memory.

    There are two types of instruction for TSX. First up is Hardware Lock Elision (HLE), a set of legacy compatible instructions that uses the XACQUIRE and XRELEASE instruction prefixes, used to specify transactional regions. Software written using this technique will run on processors with and without TSX extensions. The second software interface is Restricted Transactional Memory (RTM), which is a set of new instructions that make it far easier for a programmer to set up transactional regions. Programmers need to provide alternate code for cases where the code is run on a system without the TSX instructions.

    To summarize, when writing highly parallel applications with a lot of shared memory, TSX can make both program development and execution a lot faster. It'll be interested to see how well it works alongside some gpgpu computing if the iGPU has the power.

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