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Thread: A Closer Look Into The AMD Bulldozer..............

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    Default A Closer Look Into The AMD Bulldozer..............

    AMD is unveiling today the new processor architecture that will be used in their new CPUs starting in 2011. Codenamed Bulldozer, this architecture is completely different from the current AMD64 architecture that AMD has been using since the introduction of the very first Athlon 64 CPU back in 2003. In this tutorial we will give you an in-depth explanation of how this new architecture looks like and how it works.
    For a better understanding of how the Bulldozer architecture compares to the AMD64 architecture, we suggest you to read our Inside the AMD64 Architecture tutorial before continuing.
    The Bulldozer architecture will inherit some features introduced with the AMD64 architecture, such as the integrated memory controller and the use of the HyperTransport bus for communication between the CPU and the chipset.
    Bulldozer is the codename for the architecture, not for a specific processor. As usually happens, AMD will first release processors targeted to the server market based on this new architecture, then for the high-end desktop market, then for the mainstream desktop segment, and finally for the entry-level market.
    Although AMD didn’t say any specifics of the CPUs that will be launched, they mentioned that the first desktop CPUs based on the Bulldozer architecture will require a new CPU socket, called AM3+, which will also be compatible with current socket AM3 processors. Socket AM3+ CPUs, however, won’t be compatible with socket AM3 motherboards.
    The Bulldozer architecture will have an equivalent of the Intel Turbo Boost technology, allowing the CPU to overclock itself if you are running CPU-intensive programs and if the thermal dissipation is still within specs.
    Before talking about the internals of the Bulldozer architecture, let’s first talk about the instruction sets supported by this new architecture.

    Instruction Sets
    The Bulldozer architecture, besides being compatible with the standard x86 instructions, will support the following additional instruction sets:
    • SSE4.1 and SSE4.2
    • AVX (Advanced Vector Extensions) with two additional subsets, called XOP and FMA4
    • AES (Advanced Encryption Standard)
    • LWP (Light Weight Profiling

      But what does that mean? Let’s see.
      SSE4.1 and SSE4.2
      Finally AMD CPUs will support SSE4 instructions. Currently AMD CPUs don’t support these instruction sets, which increase speed in multimedia applications (image and video processing) that support it. Current AMD CPUs support a proprietary instruction set called SSE4a, which isn’t the same thing as SSE4.
      AVX (Advanced Vector Extensions)
      A while ago, AMD proposed an SSE5 instruction set. Because Intel decided to create its own implementation of what would be the SSE5 instructions, called AVX (Advanced Vector Extensions), AMD added this instruction set to the Bulldozer architecture.
      The AVX instructions will also be supported by forthcoming CPUs from Intel based in their Sandy Bridge architecture, and use the same SIMD (Single Instruction, Multiple Data) concept introduced with the MMX instruction set and used by the SSE (Streaming SIMD Extensions) instructions. This concept consists in using a single big register to store several small-sized data and then process all data with a single instruction, speeding up processing.
      The AVX instruction set adds 12 new instructions and increases the size of the XMM registers from 128 bits to 256 bits.
      In the Bulldozer architecture, AMD decided to add some of the instructions they had originally proposed for the SSE5 instruction set. Therefore, the AVX implementation in the Bulldozer architecture is more complete than Intel’s. These additional instructions are called the XOP and FMA4 instructions, and a detailed description can be found here. In their Bulldozer presentations AMD is announcing the AVX instruction set as “also” having the FMAC (Fused Multiply Accumulate) subset, but this subset of instructions is actually part of the XOP instructions. The “AMD 4-operand form” being announced in the AMD presentations is simply the new format used by the XOP instructions and mentioning this is also completely redundant.
      AES (Advanced Encryption Standard)
      This instruction set is already being used in the new Intel CPUs based on the “Westmere” architecture and newer (except Core i3), and consists of six new instructions to deal specifically with encryption. Intel calls this instruction set AES-NI. A detailed description of these instructions can be found here.
      LWP (Light Weight Profiling)
      The LWP instructions allow programs to easily monitor software performance, which will help developers to fine-tune programs for best performance, for example. This additional instruction set has six new instructions, and a detailed description can be found here.

      The CPU Building Block
      AMD decided to take a completely different approach in the new Bulldozer architecture. They decided to create a “dual-core” module that shares some resources (the front-end engine, the floating-point unit, and the L2 memory cache, see Figure 1) and, therefore, are not completely independent from each other.


    According to AMD this was done in order to optimize the CPU and, at the same time, cut costs. The optimization comes from the fact that on a typical multi-core CPU several units inside the CPU remain idle, and these units could be combined in the Bulldozer architecture. And since the CPU will have less units, it can be smaller, which reduces the amount of material necessary to build the CPU, reducing costs. Having less units also help saving energy and reducing the amount of generated heat.
    So while AMD will call a CPU that has one of these modules a “dual-core” CPU, in reality the CPU isn’t true a dual-core product, because there aren’t two complete and complete CPUs inside the product. The “dual-core” name in this case will be used for marketing purposes, to make sure the consumer understands that although this Bulldozer-based CPU isn’t a true “dual-core” model, it should perform like one.
    Going further, for making a “quad-core” CPU, AMD will get two of these blocks and put together, so while physically speaking the processor has actually two “CPUs” inside (two of the building blocks shown in Figure 1), and not four, AMD will still call it a “quad-core” product. In Figure 2, you can see how an “eight-core” CPU based on the Bulldozer architecture would look like.


    Let’s now take an in-depth look at the Fetch and Decode units used on the Bulldozer architecture.

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    Default Re: A Closer Look Into The AMD Bulldozer..............

    Give the source, I believe it was this

    Realworldtech

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    Default Re: A Closer Look Into The AMD Bulldozer..............

    joss effort...but should have the images too...as they are mentioned...also you should post the source...

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    Default Re: A Closer Look Into The AMD Bulldozer..............


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    Default Re: A Closer Look Into The AMD Bulldozer..............

    Quote Originally Posted by Mazhar View Post
    Give the source, I believe it was this

    Realworldtech
    well, not really...i dnt remember the xact source but mayb it was hardwaresecrets or some similar site.........

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